The present invention relates generally to semiconductor devices, and more particularly, to a semiconductor device having buried bit lines and cylindrical cell gates, and a method for manufacturing the same.
As a general rule, the density of dynamic random access memory devices (DRAMs) has quadrupled every three years. At the present time, 16 Mb DRAMs are in mass production, 64 Mb DRAMs are about to enter into mass production, and 1 Gb DRAMs are in an earlier stage of development.
The memory cell of one gigabit (1 Gb) DRAMs will occupy less than 0.3 .mu.m.sup.2 area. This is the same area needed for just the contact hole in a one mega bit (1 Mb) DRAM cell. Forming one transistor, one capacitor, and one contact hole in such a small area is exceedingly difficult.
In general, the chip surface area of semiconductor memory devices is increased by approximately 1.4 X for each 4 X increase in the cell packing density thereof, which results in an approximately 1/3 reduction in the surface area available for each memory cell. Therefore, for each new generation of semiconductor memories, it has become necessary to increase the capacitance to surface area ratio of each memory cell in order to achieve sufficiently large memory cell capacitance. Past techniques for achieving this can be broadly classified into the following three categories:
(1) decreasing the thickness of the dielectric film of the memory cell capacitors;
(2) increasing the dielectric constant of the dielectric film; and,
(3) increasing the effective area of the storage electrode of the memory cell capacitors.
With respect to the first technique enumerated above, the lower practical limit of dielectric film thickness is approximately 100 .ANG., because the reliability of the memory cells becomes unacceptably degraded when the thickness of the dielectric film is less than 100 .ANG., due to the creation of Fowler-Nordheim currents. With respect to the second technique enumerated above, the most promising high dielectric constant dielectric film material is tantalum pentoxide (Ta.sub.2 O.sub.5), which provides good coverage with respect to three-dimensional memory cell structures having a high aspect ratio. However, tantalum pentoxide exhibits a high leakage current and a low breakdown voltage in a thin film state, thus limiting its utility with respect to the ultra-high capacity memories currently under development.
Consequently, the bulk of the current development efforts have been focused on the third technique enumerated above, namely, increasing the effective area of the storage electrode of the memory cell capacitors. Historically, as the need for memory cells having a large capacitance to surface area ratio has increased in parallel with the continuing development of memories having increased cell packing densities, the structure of memory cell capacitors has evolved from planar-type capacitors to three dimensional stack-type and trench-type capacitors, culminating at the present time in a stacked trench-type capacitor which is a hybrid of the stack-type and trench-type capacitors.
Additionally, it is possible to increase cell packing density by reducing the distance between isolation regions, and by forming contact holes without using additional active area.
K. Sunouchi et al. suggest an SGT memory cell wherein all devices for the memory cell are formed in one silicon pillar isolated by matrix-like trenches (see IEDM '89, "A Surrounding Gate Transistor (SGT) cell for 64/256 Mbit DRAMs"). However, the SGT cell has the following problems.
First, the process of forming the silicon pillar and capacitor are complex. Secondly, the isolation characteristics are poor. Thirdly, there is a large possibility that a short between a capacitor plate node and a gate electrode will occur during the process for forming the gate electrode.